In read and write operations in a computer memory, an address is used which has enough possible unique values to correspond to any one of the available addressable locations in the memory space. For instance a 64 Kbyte RAM will require an address having at least a 16-bit length to allow direct access to each memory location.
A known microprocessor, e.g. an Intel.RTM. 8086 microprocessor, can utilize a multiplexed address and data bus so that a certain number of pins are shared by address and data transmissions. In the known system, every bus cycle comprises an address phase, where the address is strobed into a latch and a data phase, where the data is written to or read from a memory. Though efficient in using pins, this method of supplying an address on a limited number of pins is slow.
A known method for increasing the number of addressable locations that can be accessed with an address having a length that is less than the number of bits required for the memory space is referred to as paging. In a paging scheme, a first unique address value is generated to define a "page" of the memory. A second unique address value, called an offset, is then generated to specify an addressable location in the selected page. Paging becomes necessary when an application requires a larger address space than was originally anticipated or when insufficient addressing pins are available for transmitting an address off a chip.
Paging can be implemented in a variety of ways. For instance, it can be controlled by software by writing an address to an output device to select the appropriate page, then data can be read from or written to the selected page. Paging can also be implemented in hardware where a device recognizes that an address is not in the currently selected address space and changes the page accordingly.
There is, therefore, a need for an addressing scheme that allows for efficient access of memory using a limited address length or an economical number of pins for address transmission.